Electronic design automation (EDA) software for integrated circuit (IC) has rapidly increased in importance with the continuous scaling of semiconductor technology. An IC design software often needs various simulation steps to optimize the circuit design parameters, such as pre-layout simulation and post-layout simulation, etc. However, as the IC process technology scales into sub-100 nm, the interconnects become thinner and denser. The performance of nano-scale integrated circuits may be limited because RC delay becomes no less than MOSFET gate delay.
Various techniques have been proposed to simulate backend of line (BEOL) interconnect delay using layout parasitic extraction (LPE) tools during IC circuit design and verification. Currently, during post-layout simulation, the interconnect RC parasitic parameters are extracted by rules based on existing interconnect technology profile (ITP) using the LPE tools. However, in order to assess the parasitic RC variation, extreme ITP parameters value may needed to be used in the current method. Although this method allows IC designers to sign off a design with extreme process conditions, it limits the design margin and may cause overhead in the design.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.